PubCard - Pattern recognition in multi-synaptic photonic spiking neural networks based on a DFB-SA chip

(Peer-Reviewed) Pattern recognition in multi-synaptic photonic spiking neural networks based on a DFB-SA chip

Yanan Han 韩亚楠 ¹, Shuiying Xiang 项水英 ¹, Ziwei Song 宋紫薇 ¹, Shuang Gao 高爽 ¹, Xingxing Guo 郭星星 ¹, Yahui Zhang 张雅慧 ¹, Yuechun Shi 施跃春 ², Xiangfei Chen 陈向飞 ³, Yue Hao 郝跃 ¹

¹ State Key Laboratory of Integrated Service Networks, State Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, Xidian University, Xi'an 710071, China
中国西安西安电子科技大学综合业务网国家重点实验室宽带隙半导体技术国家重点学科实验室
² Yongjiang Laboratory, Ningbo 315202, China
中国宁波甬江实验室
³ Key Laboratory of Intelligent Optical Sensing and Manipulation, Ministry of Education, the National Laboratory of Solid State Microstructures, the College of Engineering and Applied Sciences, Institute of Optical Communication Engineering, Nanjing University, Nanjing 210023, China
中国南京南京大学光通信工程研究中心智能光传感与调控技术教育部重点实验室固体微结构物理国家重点实验室

Opto-Electronic Science, 2023-11-15

https://doi.org/10.29026/oes.2023.230021

https://www.oejournal.org/article/doi/10.29026/oes.2023.230021

Abstract

Spiking neural networks (SNNs) utilize brain-like spatiotemporal spike encoding for simulating brain functions. Photonic SNN offers an ultrahigh speed and power efficiency platform for implementing high-performance neuromorphic computing. Here, we proposed a multi-synaptic photonic SNN, combining the modified remote supervised learning with delay-weight co-training to achieve pattern classification. The impact of multi-synaptic connections and the robustness of the network were investigated through numerical simulations.

In addition, the collaborative computing of algorithm and hardware was demonstrated based on a fabricated integrated distributed feedback laser with a saturable absorber (DFB-SA), where 10 different noisy digital patterns were successfully classified. A functional photonic SNN that far exceeds the scale limit of hardware integration was achieved based on time-division multiplexing, demonstrating the capability of hardware-algorithm co-computation.